T1M
M.2 · 1× ASIC
- 8–10W/chip · published board/chip power
- Encode up to 20×1080p30 / 5×4Kp30 (vendor)
- Edge / space-constrained hosts
Video infrastructure · VPU
Controlled substitution of
the media-processing path
Controlled substitution of the media path — decode, scale, encode on VPU. Ingest, orchestration, packaging and delivery stay. Vendor-published Quadra specs; we build the operator software around them. Send the brief. 24h estimate.
Architecture
What a VPU is — and what it is not
A video processing unit takes the dense decode / scale / encode path off the general-purpose CPU. GPU engines (NVENC, Quick Sync, AMF) remain peers for graphics and AI when you need them. Heterogeneous by design: CPU = control plane; GPU = AI/graphics when required; VPU = dense video.
CPU encode
Flexible and familiar — and expensive at density. Fine for control logic, packaging and orchestration; a poor default for hundreds of simultaneous live encodes.
GPU engines
NVENC, Intel Quick Sync and AMD AMF are proven hardware encode peers. Use them where graphics/AI already live; do not invent stream counts they never published.
VPU path
ASIC-backed media processing substitutes decode → filter/scale → encode. Upstream ingest and downstream packaging stay. Rollback stays boring when the boundary is clear.
Not a partnership claim with NETINT — an engineering guide for operator software and video infrastructure the studio builds around published hardware.
End-to-end
Where the VPU sits in the pipeline
Ingest and demux remain host-side. The VPU span covers decode through encode. Mux, packaging, origin and CDN stay in your existing stack.
Decorative pipeline: VPU highlighted on decode → filter/scale → encode.
Substitution
Before / after: same edges, different middle
Slot the VPU into the media-processing middle. Keep the same upstream contracts and downstream packaging so cut-over and rollback stay operationally dull.
CPU-heavy encode block versus VPU decode–encode slot-in; packaging unchanged.
Frames
Zero-copy / hardware frames
Host YUV paths copy frames across PCIe. With decoder out=hw, frames stay on device; hardware filters require HW frames. Device selection via -dec / -enc.
Host YUV versus on-device out=hw path into the VPU.
Form factors
NETINT Quadra matrix (vendor-published)
Figures below are vendor-published product specs from netint.com — not our laboratory claims. Use them for capacity planning conversations, then measure on your ladders.
T1U
U.2 · 1× ASIC
- 17W · published board/chip power
- Encode up to 32×1080p30 / 8×4Kp30 (vendor)
- Scale-out datacenter density
T1A
AIC PCIe add-in · 1× ASIC
- 20W · published board/chip power
- Encode up to 32×1080p30 / 8×4Kp30 (vendor)
- Thermal headroom / precision cards
T2A
AIC dual-chip · 40W card
- 40W · published board/chip power
- Encode up to 64×1080p30 / 16×4Kp30 (vendor)
- Density / cost-per-stream focus
Encode codecs (vendor): H.264, HEVC, AV1, JPEG (8/10-bit). Decode: H.264, HEVC, VP9, JPEG. Integration surface: FFmpeg, GStreamer, libxcoder, Bitstreams control plane. PCIe 4.0 x4 on the migration path.
Encode (vendor)
H.264HEVCAV1JPEG
Decode (vendor)
H.264HEVCVP9JPEG
Host I/O
PCIe 4.0 x48/10-bit
Software
Inspectable encoder name change
Operators should see the encoder swap in configs and metrics — not a silent binary. FFmpeg: libx265 → h265_ni_quadra_enc; keep HW frames on device for hardware filters.
FFmpeg
Swap software encoders for Quadra names (for example h265_ni_quadra_enc). Decoder out=hw keeps frames on device; -dec / -enc select devices.
GStreamer
Pipeline elements wire the same decode → filter → encode boundary. Prefer HW memory when filters are hardware-backed.
libxcoder
Lower-level control for sessions and resources when FFmpeg wrappers are not enough for your orchestration.
Bitstreams™ control plane
Vendor control plane for fleet-facing configuration. Treat it as published integration surface — verify versions in scoping.
Migration
Controlled substitution — seven short steps
Condensed from common VPU migration practice: measure first, keep a clear frame boundary, demand feature parity (not bit-identity), and scale only on evidence.
1 · Baseline
Capture current ladder quality, density, CPU/GPU load and failure modes before touching devices.
2 · Host / software fit
Confirm PCIe generation, thermal envelope, driver/FFmpeg builds and form-factor (M.2 / U.2 / AIC).
3 · Clear frame boundary
Decide where host frames end and HW frames begin so filters and encoders share one memory contract.
4 · Feature parity ≠ bit-identity
Match required features and perceptual targets. Do not require bit-exact output versus the software path.
5 · Parallel rollback
Run VPU and legacy paths in parallel with an operator-owned cut-over and a dull rollback switch.
6 · Device monitoring
Wire ni_rsrc_mon (load, sessions, memory) beside stream-health signals before raising concurrency.
7 · Scale by evidence
Increase density only when telemetry and stream health stay inside agreed budgets.
Operations
Device telemetry meets stream health
Capacity without correlation is guesswork. Pair ASIC load with playback and ladder health so operators see cause, not just symptoms.
ni_rsrc_mon
Decoder/encoder load, session counts and memory — the device-side pulse to chart next to queue depth.
Stream health
Segment freshness, encode errors, keyframe cadence and CDN origin health stay first-class.
Correlate
When stream health dips, check device saturation before blaming packaging or CDN.
FAQ
Questions operators ask first
No partnership claim. We build operator software and video infrastructure around published hardware — including NETINT Quadra VPUs — and cite vendor specs as vendor specs.
T1M (M.2, edge), T1U (U.2, scale-out), T1A (AIC single), T2A (AIC dual-chip). Watts and stream counts above are vendor-published; validate on your ladders.
Encoder names swap (for example libx265 → h265_ni_quadra_enc). Prefer decoder out=hw so frames stay on device; hardware filters need HW frames; select devices with -dec / -enc.
Ingest, orchestration, packaging, origin and CDN delivery. The VPU substitutes the media-processing middle so rollback stays boring.
Need a VPU-ready operator path?
Send the brief — ladders, density targets, host constraints. Estimate within 24 hours.